(ZH-EN Translation by DeepSeek-V3-0324)

Background

Recently, the national key lab planned to initiate work on intelligent circuit design, and while preparing materials, we often needed circuit schematics as examples. However, there were no readily available tools to conveniently draw these schematics. Existing schematic drawing tools require manually placing each component and connecting each wire one by one. Even drawing a small-scale example involves tedious operations. For instance, a 4-bit adder contains hundreds of transistors, and manually placing components for larger examples becomes nearly as labor-intensive as designing a 4004 processor from scratch. Moreover, real synthesis and placement and routing (PNR) tools are not only cumbersome to invoke but also produce visually unappealing diagrams. As a result, I have always resorted to writing my own scripts to generate these diagrams.

Initially, I used Python with PIL (Python Imaging Library) to draw the schematics. I wrote a few basic functions to draw transistors and logic gates at specified positions, but the placement and routing still had to be designed manually, resulting in low efficiency. I then decided to add simple placement and routing logic to the script to automate the entire workflow from input circuit netlists to output schematics. Here is the final result:

For computationally intensive tasks like placement and routing, I immediately abandoned Python in favor of C++ to avoid waiting an entire day to generate a single diagram. The routing algorithm reused a maze routing implementation I had previously written for another project. I then pasted the routing code into DeepSeek and asked it to complete the placement code. DeepSeek-V3-0324 demonstrated impressive coding capabilities, producing functional and complete code that worked right away. With the help of the large language model, along with some research and clever ideas, abandoning PIL did not cause much pain. DeepSeek provided code for outputting PNGs, extracting BDF bitmap fonts, and helped debug a bug in the diagonal line rasterization algorithm.

Thus, I quickly implemented this ~800-line automated circuit placement and routing program that takes BLIF as input and outputs PNGs. It is entirely self-contained, with dependencies limited to the C++ Standard Template Library (STL). Even as someone who has been programming since childhood, this coding experience was entirely new to me, showcasing how large language models are reshaping the programming experience. Without such models, reading RFCs for PNG, BDF, DEFLATE, and writing low-level functions would have been extremely painful, and I would never have attempted it.

Abandoning Python and returning to C++ has never been easier, and presumably, the same applies to abandoning CUDA. In this era, ecosystem barriers are being weakened across the board—an exciting trend!

Code

The code uses C++26. Currently, only GCC 15.0 can compile it, but since 15.0 has not yet been released, I compiled the latest GCC from source.

This is my first extensive use of the ranges library, and the experience has been great—it often saves a lot of unnecessary verbosity. The current ranges implementation still lacks some features, such as a reverse drop (removing elements from the end of a range). It’s also inconvenient to determine whether a loop iteration is the first or last, making the old-fashioned way of writing loops sometimes preferable.

The C++ standard also lacks some key containers, such as a trie—why hasn’t this been added yet? The performance of some older containers has long been criticized, and it’s time for a refresh. The latest standard provides flat_map, but in my testing, it showed no performance advantage in my use case. I didn’t see an unordered_flat_map. Hopefully, these new features will avoid repeating the mistakes of regex.

Expand code

Here’s an analysis of the code by DeepSeek-R1:

Expand analysis
This program is a tool for generating standard CMOS circuit schematics, supporting BLIF format input and PNG image output. Below is an interpretation of its core functionality and workflow:

  1. Input Parsing (parse function)

    • Functionality: Parses the BLIF file to extract circuit input/output ports and logic gate information.
    • Key Data Structures:
      • inputs/outputs: Store input/output port IDs.
      • gates: A hash table storing logic gates, with gate IDs as keys and gate types (e.g., NOT, NAND) and their connected ports as values.
      • names: Maps gate type names to unique IDs, supporting dynamic expansion.
    • Processing Logic:
      • Parses .inputs, .outputs, and .subckt sections line by line to extract port and subcircuit information.
      • Uses the parse_name function to convert string-type gate names to integer IDs for subsequent processing.

  2. Placement Optimization (place function)

    • Algorithm: Uses simulated annealing for placement optimization, aiming to minimize routing cost and area.
    • Key Parameters:
      • initial_temperature: Controls the probability of accepting worse solutions early in the algorithm.
      • cooling_rate: Gradually reduces temperature to converge to an optimal solution.
      • area_cost and cross_track_penalty: Penalize area usage and cross-track routing, respectively.
    • Workflow:
      • Initial Placement: Randomly generates gate positions, ensuring no overlaps.
      • Iterative Optimization: Adjusts gate positions, calculates new layout costs, and accepts or rejects solutions based on the Metropolis criterion.
      • Termination: Stops when temperature drops below a threshold or after a timeout.

  3. Routing (route function)

    • Objective: Generates paths for connections between logic gates while avoiding conflicts.
    • Key Steps:
      • Obstacle Marking: Uses the mask array to mark non-routable areas (e.g., space around gates).
      • Path Search: Employs BFS to search backward from target ports to source ports, recording paths.
      • Cost Calculation: Accumulates path length and cross-track penalties.
    • Output:
      • paths: Stores coordinates of all connection paths.
      • solders: Records solder point positions.

  4. Drawing (draw_t struct)

    • Functionality: Renders the placement and routing results as a PNG image.
    • Core Methods:
      • Basic Shapes: line, ellipse for drawing lines and solder points.
      • Logic Gate Drawing: Functions like nmos, pmos, inv, nand implement CMOS gate rendering.
      • Text Labels: The text function uses predefined font bitmaps to label port names.
    • PNG Generation: Manually constructs the PNG file format (including IHDR, IDAT, IEND chunks), combines DEFLATE compression and CRC checks, and outputs the final image.

  5. Main Workflow (main function)

    • Input Parsing: Reads the BLIF file and extracts circuit information.
    • Placement Optimization: Calls place to generate the initial layout.
    • Grid Alignment: Uses snap_to_microgrid to align layout coordinates to a micro-grid.
    • Multiple Routing Attempts: Incrementally increases slackness (slackness) and calls route until successful.
    • Image Generation: After successful routing, calls draw_schematic to render the schematic and save it as a PNG.

Key Technologies and Challenges

  • Simulated Annealing: Balances global search and local optimization to avoid local minima.
  • Pathfinding Algorithm: Efficiently finds feasible paths in dynamic obstacle environments.
  • Low-Level Drawing: Directly manipulates pixel data and generates PNG-compliant files, handling compression and checksum details.

Summary

This program automates the generation of schematics from logical descriptions by parsing circuit definitions, optimizing placement, performing automatic routing, and rendering. Its core strength lies in combining algorithmic optimization (simulated annealing) with low-level graphics processing, making it suitable for rapid visualization of small-to-medium-scale CMOS circuits.

Usage

The input is a netlist in BLIF format. You can use the open-source tool Yosys to synthesize it from Verilog.

For example, I first asked DeepSeek to write a 4-bit adder as an example:

adder4.v
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module adder4 (  
    input [3:0] a,      // 4-bit input a  
    input [3:0] b,      // 4-bit input b  
    input cin,         // Carry input  
    output [3:0] sum,  // 4-bit sum output  
    output cout        // Carry output  
);  

// Implement the adder using continuous assignment  
assign {cout, sum} = a + b + cin;  

endmodule

Next, create a standard cell library. Currently, the code only supports NOT and NAND gates, so we need to instruct Yosys to use only these two cell types.

nandcell.lib
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library(demo) {  
  cell(NOT) {  
    area: 3;  
    pin(A) { direction: input; }  
    pin(Y) { direction: output;  
              function: "A'"; }  
  }  
  cell(NAND) {  
    area: 4;  
    pin(A) { direction: input; }  
    pin(B) { direction: input; }  
    pin(Y) { direction: output;  
             function: "(A*B)'"; }  
  }  
}

Launch Yosys and run the following commands: 

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read_verilog adder4.v  
hierarchy -check  
abc -liberty nandcell.lib  
synth  
splitnets -ports  
opt  
write_blif -top adder4

The last step outputs the netlist in BLIF format. Copy and save it to a file named adder4.blif.

adder4.blif
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# Generated by Yosys 0.51+104 (git sha1 c08f72b80, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)  

.model adder4  
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3] cin  
.outputs sum[0] sum[1] sum[2] sum[3] cout  
.names $false  
.names $true  
1  
.names $undef  
.subckt NOT A=a[3] Y=$abc$170$new_n15  
.subckt NOT A=b[3] Y=$abc$170$new_n16  
.subckt NOT A=a[2] Y=$abc$170$new_n17  
.subckt NOT A=b[2] Y=$abc$170$new_n18  
.subckt NOT A=a[1] Y=$abc$170$new_n19  
.subckt NOT A=b[1] Y=$abc$170$new_n20  
.subckt NOT A=a[0] Y=$abc$170$new_n21  
.subckt NOT A=b[0] Y=$abc$170$new_n22  
.subckt NOT A=cin Y=$abc$170$new_n23  
.subckt NAND A=a[3] B=b[3] Y=$abc$170$new_n24  
.subckt NAND A=a[2] B=b[2] Y=$abc$170$new_n25  
.subckt NAND A=$abc$170$new_n17 B=$abc$170$new_n18 Y=$abc$170$new_n26  
.subckt NAND A=$abc$170$new_n25 B=$abc$170$new_n26 Y=$abc$170$new_n27  
.subckt NOT A=$abc$170$new_n27 Y=$abc$170$new_n28  
.subckt NAND A=a[1] B=b[1] Y=$abc$170$new_n29  
.subckt NAND A=a[0] B=b[0] Y=$abc$170$new_n30  
.subckt NAND A=$abc$170$new_n21 B=$abc$170$new_n22 Y=$abc$170$new_n31  
.subckt NAND A=$abc$170$new_n30 B=$abc$170$new_n31 Y=$abc$170$new_n32  
.subckt NOT A=$abc$170$new_n32 Y=$abc$170$new_n33  
.subckt NAND A=cin B=$abc$170$new_n33 Y=$abc$170$new_n34  
.subckt NAND A=$abc$170$new_n30 B=$abc$170$new_n34 Y=$abc$170$new_n35  
.subckt NOT A=$abc$170$new_n35 Y=$abc$170$new_n36  
.subckt NAND A=$abc$170$new_n19 B=$abc$170$new_n20 Y=$abc$170$new_n37  
.subckt NAND A=$abc$170$new_n29 B=$abc$170$new_n37 Y=$abc$170$new_n38  
.subckt NOT A=$abc$170$new_n38 Y=$abc$170$new_n39  
.subckt NAND A=$abc$170$new_n35 B=$abc$170$new_n39 Y=$abc$170$new_n40  
.subckt NAND A=$abc$170$new_n29 B=$abc$170$new_n40 Y=$abc$170$new_n41  
.subckt NOT A=$abc$170$new_n41 Y=$abc$170$new_n42  
.subckt NAND A=$abc$170$new_n28 B=$abc$170$new_n41 Y=$abc$170$new_n43  
.subckt NAND A=$abc$170$new_n25 B=$abc$170$new_n43 Y=$abc$170$new_n44  
.subckt NOT A=$abc$170$new_n44 Y=$abc$170$new_n45  
.subckt NAND A=$abc$170$new_n15 B=$abc$170$new_n16 Y=$abc$170$new_n46  
.subckt NAND A=$abc$170$new_n24 B=$abc$170$new_n46 Y=$abc$170$new_n47  
.subckt NOT A=$abc$170$new_n47 Y=$abc$170$new_n48  
.subckt NAND A=$abc$170$new_n44 B=$abc$170$new_n48 Y=$abc$170$new_n49  
.subckt NAND A=$abc$170$new_n24 B=$abc$170$new_n49 Y=cout  
.subckt NAND A=$abc$170$new_n23 B=$abc$170$new_n32 Y=$abc$170$new_n51  
.subckt NAND A=$abc$170$new_n34 B=$abc$170$new_n51 Y=$abc$170$new_n52  
.subckt NOT A=$abc$170$new_n52 Y=sum[0]  
.subckt NAND A=$abc$170$new_n36 B=$abc$170$new_n38 Y=$abc$170$new_n54  
.subckt NAND A=$abc$170$new_n40 B=$abc$170$new_n54 Y=$abc$170$new_n55  
.subckt NOT A=$abc$170$new_n55 Y=sum[1]  
.subckt NAND A=$abc$170$new_n27 B=$abc$170$new_n42 Y=$abc$170$new_n57  
.subckt NAND A=$abc$170$new_n43 B=$abc$170$new_n57 Y=$abc$170$new_n58  
.subckt NOT A=$abc$170$new_n58 Y=sum[2]  
.subckt NAND A=$abc$170$new_n45 B=$abc$170$new_n47 Y=$abc$170$new_n60  
.subckt NAND A=$abc$170$new_n49 B=$abc$170$new_n60 Y=$abc$170$new_n61  
.subckt NOT A=$abc$170$new_n61 Y=sum[3]  
.end

Compile cirschem.cpp: g++ cirschem.cpp -std=c++26 -O3

Run: ./a.out adder4.blif

After waiting about half a minute for placement and routing to complete, the output will be saved as schematic.png.